fujitsus ce61 is a series of high-performance, cmos embedded arrays featuring full support of mixed-signal macros, as well as diffused high-speed rams, roms and a variety of other embedded functions. the ce61 series offers density and performance approaching standard cells, yet provides the time-to-market advantage of gate arrays. the e-series is optimized for pad-limited designs, and the f-series offers a cost-effective solution for core-limited designs. a fifth metal layer option is also available for area bump designs, providing over 1,000 i/o pads. featuring true 3.3v internal operation, with 3.3v, 5v and 5v tolerant i/os, the ce61 series features a very low-power consumption of 0.32w/gate/mhz. potential applications for the ce61 series include computing, graphics, communica- tions, networking, wireless, and consumer designs. features t e-series, 70m staggered pad pitch optimized for pad-limited designs frame total gates total pads ce61e71 1,584k 672 ce61e59 1,149k 576 ce61e45 784k 480 ce61e35 602k 424 ce61e25 403k 352 ce61e19 280k 304 ce61e15 193k 256 ce61e09 120k 208 ce61e08 80k 176 ce61e07 64k 160 f-series, optimized for core-limited designs frame total gates total pads ce61f80 2,026k 456 ce61f70 1,508k 400 ce61f60 1,182k 400 ce61f50 913k 352 ce61f40 664k 304 CE61F30 476k 256 ce61f20 303k 208 ce61f10 132k 144 embedded hard macro fixed layout soft macro fixed layout soft macro clock tree clk 5v i/o 5v i/o 5v i/o 5v i/o 5v i/o 3v i/o 3v i/o 3v i/o pcml 3v i/o 3v i/o 5v i/o 5v i/o 5v i/o 5v i/o 5v i/o ce61 series embedded array 0.28m l eff ? 0.28m l eff (0.35m drawn) ? propagation delay of 85 ps ? mixed-signal macrosCa/d and d/a converters ? high density diffused rams and roms ? separate core and i/o supply voltages ? i/osC5v, 3.3v and 5v tolerant ? 70m staggered pad pitch for pad-limited designs ? high performance and special i/osC311 pcml, 250 mhz lvds, pci, sstl ? analog and digital plls ? packaging optionsCqfp, hqfp, bga ? support for major third-party eda tools description t
? 1998 fujitsu microelectronics, inc. all company and product names are trademarks or registered trademarks of their respective owners. printed in the u.s.a. asic-fs-20505-7/98 ce61 series (0.28 m l eff ) embedded array mixed-signal macros d/a converters ? 8-bit, 30 mhz (video) ? 8-bit, 50 mhz (video) ? 8-bit, 220 mhz (video) ? 10-bit, 1.5 mhz (general purpose) ? 8-bit, 200 khz (general purpose) a/d converters ? 8-bit, 50 mhz (video) ? 6-bit, 300 mhz (disk drive) ? 10-bit, 20 mhz (digital communications) ? 8-bit, 400 khz (general purpose) ? 10-bit, 1 mhz (general purpose) multiplier compiler ? multiplicand (m): 4 m 32 ? multiplier (n): 4 n 32 (even numbers only) memory macros ? sram compiler: single and dual port (1 r/w, 1r), up to 72k bits per block ? rom compiler: up to 512k bits per block phase locked loops ? digital: 180 to 360 mhz ? analog: 50 to 200 mhz i/os ? 5v, 3.3v and 5v tolerant ? slew-rate controlled ? cmos, ttl, pcml/pecl, lvds, pci, sstl, 1284, gtl+ ips and mega macros to achieve the highest level of integration for our cus- tomers, fujitsu offers a rich set of intellectual properties (ips), developed either internally or acquired through strategic relationships with ip providers. interface functions ? arc: 32-bit embedded core ? oakdspcore ? : 16-bit fixed point dsp core ? pci core ? 10/100 ethernet mac ? p1394 ? usb high-performance functions ? mpeg2 (q1 99) ? 16/64/256 qam (q1 99) ? qpsk (q1 99) asic design kit and eda support verifire vcs, verilog-xl, (vcs, cadence tools, sign-off simulation, veritime, synopsys, synthesis) verifault, design compiler (synopsys) vhdlfire all vital compliance tools, sign-off simulation, design time, design compiler other eda tools motive, sunrise, hld, designpower package availability no. of pins frame size qfp package (1.0, 0.8, 0.65 mm pitch) 64 f10 80 f10 100 f10 120 f10, e7/8/9/15/19/25/35/45 160 e7/8/9/15/19/25/35/45/59, f20/30/40/50/60/70/80 shrink qfp package (0.5 mm pitch) 64 e7/8/9, f10 80 e7/8/9, f10 100 e9/15, f10 120 e7/8/9/15/19/25/35/45, f10 144 e7/8/9/15/19/25/35/45, f20/30/40/50 176 e8/9/15/19/25/35/45, f20/30/40/50 208 e9/15/19/25/35/45/59, f20/30/40/50/60/70/80 240 e15/19/25/35/45/59, f30/40/50/60/70 256 f40/50/60/70/80 304 f50/60/70/80 256 (0.4 mm) e19/25/35/45/59 heatspreader qfp package (0.5 mm pitch) 208 e9/15/19/25/35/45/59/71, f20/30/40/50/60/70/80 240 e15/19/25/35/45/58/71, f30/40/50/60/70/80 256 f40/50/60/70/80 304 e35/45/59/71, f50/60/70/80 256 (0.4 mm) e19/25/35/45/59/71 ball grid array (1.27 mm pitch) 256 e15/19, f40/50 352 e25/35, f60/70 420 e35/45, f60/70 576 e45/59 672 e71 fujitsu microelectronics, inc. corporate headquarters 3545 north first street, san jose, california 95134-1804 tel: (800) 866-8608 fax: (408) 922-9179 e-mail: fmicrc@fmi.fujitsu.com internet: http://www.fujitsumicro.com
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